1. Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for reducing color conflicts during trim generation for masks to be used in an optical lithography process for manufacturing an integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9cretical.xe2x80x9d) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focussed through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem in performing the optical lithography process arises from conflicts between phase shifters. Phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer through the mask. During phase shifting, destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask""s clear regions exhibits a wave characteristic having a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t1 and the other of thickness t2, one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t1 and t2 appropriately, the light exiting the material of thickness t2 is 180 degrees out of phase with the light exiting the material of thickness t1. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled xe2x80x9cPhase Shifting Circuit Manufacture Method and Apparatus,xe2x80x9d by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999, which is hereby incorporated by reference.
As can be seen in FIG. 1A, when two phase shifters are located in close proximity to each other, conflicts can arise. In FIG. 1A, a first phase shifter comprising a zero-degree phase region 102 and a 180-degree phase region 104 is used to produce a small line width in a gate region 103 of polysilicon line 101. Similarly, a second phase shifter comprising a zero-degree phase region 114 and a 180-degree phase region 112 is used to produce a small line width in a gate region 113 of polysilicon line 111.
Unfortunately, when the first phase shifter and the second phase shifter are located in close proximity to each other, conflicts can arise between them as is illustrated in FIG. 1A. In existing systems, this can cause the system to halt with a phase conflict error.
What is needed is a method and an apparatus for resolving conflicts between phase shifters.
Another problem arises during the process of generating phase shifters and associated trim. A phase shifter located on a phase shifting mask will often be generated along with associated trim located on a second mask. During exposure of the second mask, this trim protects a region that is to be exposed by the phase shifter during exposure of the phase shifting mask. Unfortunately, design rules typically cause patches to be added to the shifter and to the associated trim and these patches can cause conflicts with other features on the masks. Note that in existing systems, phase shift regions cannot overlap with field polysilicon.
What is needed is a method and an apparatus for generating phase shifters and trim that satisfy design rules while minimizing conflicts with other mask features.
One embodiment of the invention provides a system for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit. The system operates by identifying a feature within the integrated circuit to be created by using a phase shifter to produce a region of destructive light interference on a photoresist layer. Next, the system generates the phase shifter for a first mask, while ensuring that design rules are satisfied in defining dimensions for the phase shifter. After the phase shifter is generated, the system generates trim within a second mask, that is used in conjunction with the first mask, by deriving the trim from the previously-defined dimensions of the phase shifter while ensuring that the design rules are satisfied. Note that the design rules can be satisfied by cutting and/or patching portions of the phase shifter and associated trim. In some instances patching may be necessary in combination with cutting in order to ensure that other requirementsxe2x80x94e.g. minimum trim sizexe2x80x94can be satisfied.
In one embodiment of the invention, the phase shifter in the first mask is used to expose a first polysilicon line in a gate region of the integrated circuit. Furthermore, the trim in the second mask is used to protect the first polysilicon line from exposure during use of the second mask.
In one embodiment of the invention, ensuring that the design rules are satisfied involves ensuring that there exists a minimum spacing between the trim and a second polysilicon line in the integrated circuit.
In one embodiment of the invention, ensuring that the design rules are satisfied involves ensuring that the trim is covered by the phase shifter in the first mask. It also involves ensuring that the phase shifter extends a minimum distance beyond the trim. In a variation on this embodiment, ensuring that the phase shifter extends the minimum distance beyond the trim involves ignoring the minimum distance in areas where the trim is connected to a wire.
In one embodiment of the invention, generating the phase shifter involves adding a patch to the phase shifter in order to satisfy a design rule.
In one embodiment of the invention, generating the phase shifter involves reducing the size of the phase shifter instead of adding a patch to the phase shifter in order to satisfy a design rule.
In one embodiment of the invention, ensuring that design rules are satisfied involves ensuring that inter-cell design rules are satisfied.
In one embodiment of the invention, ensuring that design rules are satisfied involves ensuring that intra-cell design rules are satisfied.
In one embodiment of the invention, the system additionally identifies a conflict area wherein a conflict is likely to occur between a first phase shifter and a second phase shifter on the first mask. When the conflict area is identified, the system resolves the conflict by cutting back one or both of the first phase shifter and the second phase shifter, so that the first phase shifter and the second phase shifter do not interfere with each other in the conflict area.